Per
Stenström, Professor,
computer architecture
Fellow of the
ACM and the IEEE
Member of the
Royal Swedish Academy of Engineering Sciences
Member of
Academia Europaea
Check
out our newly published textbook in Computer Architecture
Research summary
Present and former Ph. D. students
I'm a
professor of computer engineering at Chalmers University of Technology since 1995 where I teach
and manage a research program in computer architecture. I'm also interested in the interplay between
research and innovation processes. To this end, I am on the board of Chalmers Innovation
and involved in a number of initiatives to promote entrepreneurship. I am also
working on the establishment of EuReCCA - a
pan-European virtual center in Computer Systems Architecture
Before coming
to Chalmers I was on the faculty of Lund
University where I received my MSc in Electrical Engineering and Ph D in Computer Engineering. My research program centers
on computer architecture with a current research emphasis on design principles
for chip multiprocessors (or multicores as many refer to them). My publications in
the past include more than a hundred published papers and three textbooks. I
have been a visiting scientist at Carnegie Mellon University (1987-1988), Stanford University (1991),
and University of Southern
California (1993) and in 2003, I spent a sabbatical leave at Sun Microsystems. I'm
Associate Editor-in-Chief of Journal of Parallel and Distributed Computing and
Senior Associate Editor of ACM Transactions on Architecture and Code
Optimization (TACO). I am regularly serving program committees for computer
architecture and parallel processing conferences. I have also acted as program
and general chair for a number of conferences. I was general chair of the 28th
Annual International Symposium on Computer Architecture (ISCA) in 2001 and
program chair of the same symposium in 2004. In 2008 I was program co-chair of
the IEEE International Symposium on High-Performance Computer Architecture
(HPCA) held in Salt Lake City and in 2009 I was the program chair for the IEEE
IPDPS held in Rome. I am a co-founder of the International Conference on
High-Performance and Embedded Architectures and Compilers and acted as its
general co-chair in 2008 and program co-chair for the same in 2007 and am now
Steering Committee chair for this conference series. I am also spending a
considerable amount of time as a co-founding partner of the HiPEAC network. I'm a
Fellow of the IEEE and a member of the IEEE Computer Society. I am also a
Fellow of the ACM, and member of SIGARCH. Since 2009 I am a member of the Royal
Swedish Academy of Engineering Sciences and since 2010 of the Academia
Europaea. For more details about my accomplishments, consult my CV .
Computer
industry has embarked on the multicore roadmap that predicts a doubling of the
number of processor cores on a chip every two years. While we will see a gradual
adaptation on the software side to parallel applications in the next ten years,
parallel applications will have serial sections that will limit scalability. In
addition, memory bandwidth will have to scale at the same pace as computational
speed, the performance of on-chip memory hierarchies will be critical to
scaling computational performance. For these reasons, it is not clear
what the architecture of the processor cores as well as the on-chip memory
system should look like in ten years from now. Not only must they be able to
scale computational performance at the rate we have got used to, they have to
do it within a power budget that will only increase modestly over the next ten
years. The research in the High-Performance Computer Architecture Group
at Chalmers is oriented towards processor and memory system architectures for
future microprocessor. We have studied design principles for multiprocessor
architectures for more than two decades with an emphasis on memory system
design. While this is still one of our focuses, the one of the most pressing
problem is how to make multicore architectures useful to the software. To this
end, our current focus is on new architectural abstractions that will make it
easier for the software to extract thread-level parallelism. A transactional
memory system is such an abstraction that we work on. We are also looking
into innovative approaches to design on-chip memory hierarchies that make
better use of memory resources. In addition, we work on performance-tuning methodologies
for large-scale multithreaded software.
Ph. D.
Theses under my supervision:
Licentiate
students under my supervision: (A Swedish degree that is half-way between M.Sc. and Ph. D.
degree.)
I am teaching
the computer architecture course (DAT105) in the 2012/2013 academic year
·
Associate
Editor-in-Chief (in parallel and
distributed computer architecture) of Journal of Parallel and Distributed Computing
·
Senior Associate Editor
of ACM TACO (Transactions on
Architecture and Code Optimization)
·
Organizer of the Sixth Workshop on Programmability issues for Multi-Core Computers
(MULTIPROG)
·
Program
committee member for the 39th IEEE/ACM International Symp. on
Computer Architecture. ISCA
2012
·
Program
committee member for the 19th IEEE High-Performance Computer Architecture. HPCA 2013
·
My
family, i.e., my wife Carina and our wonderful girl Sofia.
·
Sailing.
We just got our dream boat - a Comfort 32.
·
Jazz.
One of my favorites is Pat Metheny
·
Wine
tasting. One of my favorite wine centers in the world is Sonoma
Email:
pers@chalmers.se
Office address:
Department of Computer Science and Engineering
Chalmers
University of Technology
S-412 96 Gothenburg, SWEDEN
+46-31-772 1761 (phone)
+46-31-772 3663 (fax)
+46-730 346 340 (mobile phone)
Visiting
address: Rännvägen 6
Per
Stenström < pers@chalmers.se>
2012-11-26