Per
Stenström, Professor,
computer architecture
Fellow of the
ACM and the IEEE
Member of the
Royal Swedish Academy of Engineering Sciences
Member of
Academia Europaea
Check
out our newly published textbook in Computer Architecture
Table
of contents:
Research summary
Present and former Ph. D. students
About
me
I'm a
professor of computer engineering at Chalmers University of Technology since 1995 where I teach
and manage a research program in computer architecture. I'm also interested in the interplay between
research and innovation processes. To this end, I am on the board of Chalmers Innovation
and involved in a number of initiatives to promote entrepreneurship. I am also
working on the establishment of EuReCCA - a
pan-European virtual center in Computer Systems Architecture
Before coming
to Chalmers I was on the faculty of Lund
University where I received my MSc in Electrical Engineering and Ph D in Computer Engineering. My research program centers
on computer architecture with a current research emphasis on design principles
for chip multiprocessors (or multicores as many refer to them). My publications in
the past include more than a hundred published papers and three textbooks. I
have been a visiting scientist at Carnegie Mellon University (1987-1988), Stanford University (1991),
and University of Southern
California (1993) and in 2003, I spent a sabbatical leave at Sun Microsystems. I'm
Associate Editor-in-Chief of Journal of Parallel and Distributed Computing and
Senior Associate Editor of ACM Transactions on Architecture and Code
Optimization (TACO). I am regularly serving program committees for computer
architecture and parallel processing conferences. I have also acted as program
and general chair for a number of conferences. I was general chair of the 28th
Annual International Symposium on Computer Architecture (ISCA) in 2001 and
program chair of the same symposium in 2004. In 2008 I was program co-chair of
the IEEE International Symposium on High-Performance Computer Architecture
(HPCA) held in Salt Lake City and in 2009 I was the program chair for the IEEE
IPDPS held in Rome. I am a co-founder of the International Conference on
High-Performance and Embedded Architectures and Compilers and acted as its
general co-chair in 2008 and program co-chair for the same in 2007 and am now
Steering Committee chair for this conference series. I am also spending a
considerable amount of time as a co-founding partner of the HiPEAC network. I'm a
Fellow of the IEEE and a member of the IEEE Computer Society. I am also a
Fellow of the ACM, and member of SIGARCH. Since 2009 I am a member of the Royal
Swedish Academy of Engineering Sciences and since 2010 of the Academia
Europaea. For more details about my accomplishments, consult my CV .
Research summary
Computer
industry has embarked on the multicore roadmap that predicts a doubling of the
number of processor cores on a chip every two years. While we will see a gradual
adaptation on the software side to parallel applications in the next ten years,
parallel applications will have serial sections that will limit scalability. In
addition, memory bandwidth will have to scale at the same pace as computational
speed, the performance of on-chip memory hierarchies will be critical to
scaling computational performance. For these reasons, it is not clear
what the architecture of the processor cores as well as the on-chip memory
system should look like in ten years from now. Not only must they be able to
scale computational performance at the rate we have got used to, they have to
do it within a power budget that will only increase modestly over the next ten
years. The research in the High-Performance Computer Architecture Group
at Chalmers is oriented towards processor and memory system architectures for
future microprocessor. We have studied design principles for multiprocessor
architectures for more than two decades with an emphasis on memory system
design. While this is still one of our focuses, the one of the most pressing
problem is how to make multicore architectures useful to the software. To this
end, our current focus is on new architectural abstractions that will make it
easier for the software to extract thread-level parallelism. A transactional
memory system is such an abstraction that we work on. We are also looking
into innovative approaches to design on-chip memory hierarchies that make
better use of memory resources. In addition, we work on performance-tuning methodologies
for large-scale multithreaded software.
Research projects
- CHAMPP.
Chalmers Adaptive Multiprocessing Project
- HiPEAC network. High-Performance and Embedded Architectures and
Compilers
Present and former Ph. D. students
Present
Ph. D. students:
- Angelos Arelakis, MSc, PhD student
- Tobias Fjälling, MSc, PhD student
- Jochen Hollman, Lic tech., PhD student
- Nima
Namaki, Lic tech,
PhD student
- Madhavan Mannivanan, MSc, PhD student
- Anurag
Negi,
Lic tech, PhD student
- Andras Vajda, MSc, Ericsson
industrial PhD student
Former
Ph. D. students:
Graduated
Licentiate and Ph. D. Students
Ph. D.
Theses under my supervision:
- Mats Brorsson: "Performance Impact of Shared
Memory Latency in Multiprocessors: Models and Experiments," Ph. D.
thesis, Department of Computer Engineering, Lund University, May 1994.
First employment Assist. prof. Lund Univeristy.
- Fredrik Dahlgren: "Design and Performance
Evaluation of Hardware-Based Cache Protocol Extensions for
Multiprocessors," Ph. D. thesis, Department of Computer Engineering,
Lund University, November 1994. First employment: Assist. res. prof. Lund
University.
- Håkan Grahn: "Evaluation of Design Alternatives
for a Directory-Based Cache Coherence Protocol in Shared-Memory
Multiprocessors," Ph. D. thesis, Department of Computer Engineering,
Lund University, December 1995. First employment: Assist. prof. University
of Karlskrona/Ronneby.
- Jonas Skeppstedt: "Compiler Based Approaches to
Reduce Memory Access Penalties in Cache-Coherent Multiprocessors,"
Ph. D. thesis, Department of Computer Engineering, Chalmers University of
Technology, May 1997. First employment: Assist. prof., Halmstad
University.
- Magnus Karlsson: "Data Prefetching Techniques
Targeting Single and a Network of Processing Nodes". Ph. D. thesis,
Department of Computer Engineering, Chalmers University of Technology,
December 1999. First employment: Hewlett Packard Laboratories, Palo Alto.
- Ashley Saulsbury: "Attacking Latency Bottlenecks
in Distributed Shared Memory Systems," Ph.D. thesis, Department of
Teleinformatics, the Royal Institute of Technology, Stockholm, December
1999. First employment: Sun Microsystems, Menlo Park.
- Thomas Lundqvist: "A WCET Analysis Method for
Pipelined Microprocessors and Cache Memories", Ph. D. thesis, Department
of Computer Engineering, Chalmers University of Technology, June 2002.
First employment: Assist. professor, IT-University of Gothenburg
- Jim Nilsson: "Towards Accurate and
Resource-Efficient Cache Coherence Prediction", Ph. D. thesis, Department
of Computer Engineering, Chalmers University of Technology, January 2004.
First employment: Independent consultant
- Magnus Ekman: "Strategies to Reduce Energy and
Resources in Chip Multiprocessor Systems", PhD thesis, Department of
Computer Science and Engineering, Chalmers University of Technology,
December 2004.. First employment: Sun Microsystems
- Fredrik Warg: "Techniques to Reduce Thread-Level
Speculation Overhead" PhD thesis, Department of Computer Science and
Engineering, Chalmers University of Technology, June 2006. First
employment: Startup company.
- Martin Thuresson: "Compression Techniques to
Improve Bandwidth and Code Size in Computer Systems" PhD thesis,
Department of Computer Science and Engineering, Chalmers University of
Technology, September 2008. First employment. Google Corp. Mountain View.
- M. M. Waliullah. “Performance Optimization Techniques
for Hardware Transactional Memory” Ph. D. thesis. Department of Computer
Science and Engineering, Chalmers University of Technology, February 2011.
First employment: INRIA, Rennes, France.
- Mafijul Md. Islam. “Techniques to Cancel Execution
Early to Improve Processor Efficiency”. Ph. D thesis. Department of
Computer Science and Engineering, Chalmers University of Technology, June
2011. First employment: Volvo Technology.
Licentiate
students under my supervision: (A Swedish degree that is half-way between M.Sc. and Ph. D.
degree.)
- Ulf Assarsson: "View Frustum Culling and Animated
Ray Tracing: Improvements and Methodological Considerations", Licentiate
thesis. May 2001.
- Jonas Jalminger. "On Improving Data Cache Space
Utilization", Licentiate thesis (main advisor), Jan 2002.
- Martin Kampe. "Prediction Methods for Cache and
Branch Management in Computers, Licentiate thesis, May 2002.
- Peter Rundberg. "Data Dependence Speculation
Methods to Expose Thread-Level Parallelism, Nov 2002.
- Jochen Hollman “Latency Reduction and Tolerance in
Distributed Digital Libraries”, Sept 2003
- Nima Namaiki. "Exhaustion Dominated Performance:
Methodology, Tools, and Empirical Experiments", December 2008
Teaching
I am teaching
the computer architecture course (DAT105) in the 2012/2013 academic year
Professional Services and Activites
(2009-2010)
·
Associate
Editor-in-Chief (in parallel and
distributed computer architecture) of Journal of Parallel and Distributed Computing
·
Senior Associate Editor
of ACM TACO (Transactions on
Architecture and Code Optimization)
·
Organizer of the Sixth Workshop on Programmability issues for Multi-Core Computers
(MULTIPROG)
·
Program
committee member for the 39th IEEE/ACM International Symp. on
Computer Architecture. ISCA
2012
·
Program
committee member for the 19th IEEE High-Performance Computer Architecture. HPCA 2013
The Best Part of My Life!!!
·
My
family, i.e., my wife Carina and our wonderful girl Sofia.
·
Sailing.
We just got our dream boat - a Comfort 32.
·
Jazz.
One of my favorites is Pat Metheny
·
Wine
tasting. One of my favorite wine centers in the world is Sonoma
Address information
Email:
pers@chalmers.se
Office address:
Department of Computer Science and Engineering
Chalmers
University of Technology
S-412 96 Gothenburg, SWEDEN
+46-31-772 1761 (phone)
+46-31-772 3663 (fax)
+46-730 346 340 (mobile phone)
Visiting
address: Rännvägen 6
Per
Stenström < pers@chalmers.se>
2012-11-26