Address information
I'm a professor of computer engineering at
Chalmers University of Technology
since 1995 where I teach and manage research in computer architecture. Two
years back, I started a company (Nema Labs)
to meet the challenges that multi-core architectures impose on the program
development community.
I was previously on the faculty of
Lund University
where I received
my MS in EE and Ph. D. in CE. My research program centers on computer
architecture with a current research emphasis on design principles for chip
multiprocessors or multicores as many refer to them. My
publications
in the past include more than a hundred published papers and two textbooks.
I have been a visiting scientist at
Carnegie Mellon University (1987-1988),
Stanford University (1991), and
University of Southern California (1993)
and most recently (2003), I spent my sabbatical leave at Sun Microsystems.
I'm on the editorial board of of
Journal of Parallel and Distributed Computing, the IEEE Computer
Architecture Letters, the IEEE Transactions on Parallel and Distributed Systems, and am the founding editor-in-chief of Transactions on
HiPEAC. I have served about 50
program committees for computer architecture and parallel processing
conferences over the last ten years. I have also acted as program and general
chair for a number of conferences. I was general chair of the 28th Annual International Symposium on
Computer Architecture (ISCA) in 2001 and program chair of the same symposium in 2004. In 2008 I was program co-chair of
the IEEE International Symposium on High-Performance Computer Architecture (HPCA) held in Salt Lake City and in 2009
I was the program chair for the IEEE IPDPS held in Rome. Earlier, I was
general co-chair for the International Conference on High-Performance and
Embedded Architectures and Compilers in 2008 and program co-chair for the same
in 2007 and am now Steering Committee chair for this conference series. I'm a Fellow of the IEEE and a member of the IEEE Computer Society.
I am also a Fellow of the ACM, and member of SIGARCH. In 2009 I became a member of the Royal Swedish
Academy of Engineering Sciences. For more details about my accomplishments,
consult my CV .
Computer architecture will continue to be driven by the performance demands of emerging
applications. At one extreme such applications are exemplified by retrieving information
from huge databases and scientific computational problems. At another extreme,
mobile computing systems demand a high performance but are also severely constrained by resources and limited
battery-capacity. The research in the High-Performance Computer Architecture Group
at Chalmers is oriented towards processor and memory system architectures for high-performance embedded systems.
We have studied design principles for multiprocessor architectures for more than
two decades with an emphasis on memory system design. While this is still our
focus, the most pressing problem is how to make multicore architectures useful
to the software. To this end, our current focus is on new architectural
abstractions that will make it easier for the software to extract thread-level
parallelism. Transactional memory systems is such an abstraction that we work on.
Present Ph. D. students:
-
Jochen Hollman,
Lic tech., PhD student
-
Mafijul Md. Islam, Lic tech,
PhD student
-
Nima Namaki, Lic
tech, PhD student
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Anurag Negi, MSc, PhD student
-
M.M. Waliullah, Lic tech, PhD student
Former Ph. D. students:
Graduated Licentiate and Ph. D. Students
Ph. D. Theses under my supervision:
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Mats Brorsson: "Performance Impact of Shared Memory Latency in Multiprocessors: Models and Experiments," Ph. D. thesis, Department of Computer Engineering, Lund University, May 1994. First employment Assist. prof. Lund Univeristy.
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Fredrik Dahlgren: "Design and Performance Evaluation of Hardware-Based Cache Protocol Extensions for Multiprocessors," Ph. D. thesis, Department of Computer Engineering, Lund University, November 1994. First employment: Assist. res. prof. Lund University.
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Håkan Grahn: "Evaluation of Design Alternatives for a Directory-Based Cache Coherence Protocol in Shared-Memory Multiprocessors," Ph. D. thesis, Department of Computer Engineering, Lund University, December 1995. First employment: Assist. prof. University of Karlskrona/Ronneby.
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Jonas Skeppstedt: "Compiler Based Approaches to Reduce Memory Access Penalties in Cache-Coherent Multiprocessors," Ph. D. thesis, Department of Computer Engineering, Chalmers University of Technology, May 1997. First employment: Assist. prof., Halmstad University.
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Magnus Karlsson: "Data Prefetching Techniques Targeting Single and a Network of Processing Nodes". Ph. D. thesis, Department of Computer Engineering, Chalmers University of Technology, December 1999. First employment: Hewlett Packard Laboratories, Palo Alto.
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Ashley Saulsbury: "Attacking Latency Bottlenecks in Distributed Shared Memory Systems," Ph.D. thesis, Department of Teleinformatics, the Royal Institute of Technology, Stockholm, December 1999. First employment: Sun Microsystems, Menlo Park.
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Thomas Lundqvist: "A WCET Analysis Method for Pipelined Microprocessors and Cache Memories", Ph. D. thesis, Department of Computer Engineering, Chalmers University of Technology, June 2002.
First employment: Assist. professor, IT-University of Gothenburg
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Jim Nilsson: "Towards Accurate and Resource-Efficient
Cache Coherence Prediction", Ph. D. thesis, Department of Computer
Engineering, Chalmers University of Technology, January 2004. First employment:
Independent consultant
-
Magnus Ekman: "Strategies to Reduce Energy and Resources in Chip Multiprocessor
Systems", PhD thesis, Department of Computer Science and Engineering, Chalmers
University of Technology, December 2004.. First employment: Sun Microsystems
-
Fredrik Warg: "Techniques to Reduce Thread-Level Speculation Overhead" PhD
thesis, Department of Computer Science and Engineering, Chalmers University of
Technology, June 2006. First employment: Startup company.
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Martin Thuresson: "Compression Techniques to Improve Bandwidth and Code Size in
Computer Systems" PhD thesis, Department of Computer Science and Engineering,
Chalmers University of Technology, September 2008. First employment. Google
Corp. Mountain View.
Licentiate students under my supervision: (A
Swedish degree that is half-way between M.Sc. and Ph. D. degree.)
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Ulf Assarsson: "View Frustum Culling and Animated Ray Tracing: Improvements and Methodological Considerations", Licentiate thesis. May 2001.
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Jonas Jalminger. "On Improving Data Cache Space Utilization", Licentiate thesis (main advisor), Jan 2002.
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Martin Kampe. "Prediction Methods for Cache and Branch Management in Computers, Licentiate thesis, May 2002.
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Peter Rundberg. "Data Dependence Speculation Methods to Expose Thread-Level Parallelism, Nov 2002.
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Jochen Hollman “Latency Reduction and Tolerance in Distributed Digital Libraries”,
Sept 2003
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Martin Thuresson “Compression Techniques for Code Size and Data Bandwidth
Reduction" April 2006
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Md. Mafijul Islam. “Improving Execution Efficiency by Targeting Redundancy and
Parallelism”, November 2007
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M. M. Waliullah. “Schemes for Improving the Efficiency of Hardware Transactional
Memory”, January 2008
-
Nima Namaiki. "Exhaustion Dominated Performance: Methodology, Tools, and
Empirical Experiments", December 2008
I am teaching the computer architecture course (DAT105) in the 2009/2010 academic year
Editor-in-chief
of Transactions on HiPEAC
Associate
editor
of IEEE Computer Architecture
Letters
Subject-area editor of
Journal of Parallel and Distributed Computing
Associate editor of
IEEE Transactions on Parallel and Distributed Systems
Program chair for the 23rd IEEE International Parallel and Distributed
Processsing Symposium. IPDPS 2009
Program committee member for the 18th IEEE International Conf. on Parallel Architectures and
Compilation Techniques. PACT 2009
Organizer of the Third Workshop on Programmability issues for Multi-Core Computers (MULTIPROG)
Program committee member for the 37th IEEE/ACM International Symp. on Computer Architecture.
ISCA 2010
