Home page of Per Stenstrom

Per Stenström, Professor, computer architecture

Fellow of the ACM and the IEEE

Member of the Royal Swedish Academy of Engineering Sciences

Member of Academia Europaea

About me

I'm a professor of computer engineering at Chalmers University of Technology since 1995 where I teach and manage a research program in computer architecture. On the entrepreneurial side, I founded Nema Labs in 2007 to meet the challenges that multi-core architectures impose on the program development community. I am also on the board of Chalmers Innovation.

I was previously on the faculty of Lund University where I received my MS in EE and Ph. D. in CE. My research program centers on computer architecture with a current research emphasis on design principles for chip multiprocessors or multicores as many refer to them. My publications in the past include more than a hundred published papers and three textbooks. I have been a visiting scientist at Carnegie Mellon University (1987-1988), Stanford University (1991), and University of Southern California (1993) and in 2003, I spent a sabbatical leave at Sun Microsystems. I'm Associate Editor-in-Chief of Journal of Parallel and Distributed Computing and Associate Editor of ACM Transactions on Architecture and Code Optimization (TACO). I am regularly serving program committees for computer architecture and parallel processing conferences. I have also acted as program and general chair for a number of conferences. I was general chair of the 28th Annual International Symposium on Computer Architecture (ISCA) in 2001 and program chair of the same symposium in 2004. In 2008 I was program co-chair of the IEEE International Symposium on High-Performance Computer Architecture (HPCA) held in Salt Lake City and in 2009 I was the program chair for the IEEE IPDPS held in Rome. Earlier, I was general co-chair for the International Conference on High-Performance and Embedded Architectures and Compilers in 2008 and program co-chair for the same in 2007 and am now Steering Committee chair for this conference series. I am also spending a considerable time as a co-founding partner of the HiPEAC network. I'm a Fellow of the IEEE and a member of the IEEE Computer Society. I am also a Fellow of the ACM, and member of SIGARCH. Since 2009 I am a member of the Royal Swedish Academy of Engineering Sciences and since 2010 I am member of Academia Europaea. For more details about my accomplishments, please consult my CV .

Research summary

Computer industry has embarked on the multicore roadmap that predicts a doubling of the number of processor cores on a chip every eighteen months. While we will see a gradual adaptation on the software side to parallel applications in the next ten years, parallel applications will have serial sections that will limit scalability. In addition, memory bandwidth will have to scale at the same pace as computational speed, the performance of on-chip memory hierarchies will be critical to scaling computational performance. For these reasons, it is not clear what the architecture of the processor cores as well as the on-chip memory system should look like in ten years from now. Not only must they be able to scale computational performance at the rate we have got used to, they have to do it within a power budget that will only increase modestly over the next ten years. The research in the High-Performance Computer Architecture Group at Chalmers is oriented towards processor and memory system architectures for future microprocessor. We have studied design principles for multiprocessor architectures for more than two decades with an emphasis on memory system design. While this is still our focus, one of the most pressing problem is how to make multicore architectures useful to the software. To this end, our current focus is on new architectural abstractions that will make it easier for the software to extract thread-level parallelism. A transactional memory system is such an abstraction that we work on. We are also looking into innovative approaches to design on-chip memory hierarchies that make better use of memory resources. In addition, we work on performance-tuning methodologies for large-scale multithreaded software.

Research projects

CHAMPP. Chalmers Adaptive Multiprocessing Project
VELOX. Transactional memory system implementations.
HiPEAC network. High-Performance and Embedded Architectures and Compilers

Present and former Ph. D. students

Present Ph. D. students:

Angelos Arelakis, MSc, PhD student
Tobias Fjälling, MSc, PhD student
Jochen Hollman, Lic tech., PhD student
Mafijul Md. Islam, Lic tech, PhD student
Nima Namaki, Lic tech, PhD student
Madhavan Mannivanan, MSc, PhD student
Anurag Negi, Lic. Tech., PhD student
Andras Vajda, MSc, PhD student

Former Ph. D. students:

Graduated Licentiate and Ph. D. Students

Ph. D. Theses under my supervision:

Mats Brorsson: "Performance Impact of Shared Memory Latency in Multiprocessors: Models and Experiments," Ph. D. thesis, Department of Computer Engineering, Lund University, May 1994. First employment Assist. prof. Lund Univeristy.
Fredrik Dahlgren: "Design and Performance Evaluation of Hardware-Based Cache Protocol Extensions for Multiprocessors," Ph. D. thesis, Department of Computer Engineering, Lund University, November 1994. First employment: Assist. res. prof. Lund University.
Håkan Grahn: "Evaluation of Design Alternatives for a Directory-Based Cache Coherence Protocol in Shared-Memory Multiprocessors," Ph. D. thesis, Department of Computer Engineering, Lund University, December 1995. First employment: Assist. prof. University of Karlskrona/Ronneby.
Jonas Skeppstedt: "Compiler Based Approaches to Reduce Memory Access Penalties in Cache-Coherent Multiprocessors," Ph. D. thesis, Department of Computer Engineering, Chalmers University of Technology, May 1997. First employment: Assist. prof., Halmstad University.
Magnus Karlsson: "Data Prefetching Techniques Targeting Single and a Network of Processing Nodes". Ph. D. thesis, Department of Computer Engineering, Chalmers University of Technology, December 1999. First employment: Hewlett Packard Laboratories, Palo Alto.
Ashley Saulsbury: "Attacking Latency Bottlenecks in Distributed Shared Memory Systems," Ph.D. thesis, Department of Teleinformatics, the Royal Institute of Technology, Stockholm, December 1999. First employment: Sun Microsystems, Menlo Park.
Thomas Lundqvist: "A WCET Analysis Method for Pipelined Microprocessors and Cache Memories", Ph. D. thesis, Department of Computer Engineering, Chalmers University of Technology, June 2002. First employment: Assist. professor, IT-University of Gothenburg
Jim Nilsson: "Towards Accurate and Resource-Efficient Cache Coherence Prediction", Ph. D. thesis, Department of Computer Engineering, Chalmers University of Technology, January 2004. First employment: Independent consultant
Magnus Ekman: "Strategies to Reduce Energy and Resources in Chip Multiprocessor Systems", PhD thesis, Department of Computer Science and Engineering, Chalmers University of Technology, December 2004.. First employment: Sun Microsystems
Fredrik Warg: "Techniques to Reduce Thread-Level Speculation Overhead" PhD thesis, Department of Computer Science and Engineering, Chalmers University of Technology, June 2006. First employment: Nema Labs AB.
Martin Thuresson: "Compression Techniques to Improve Bandwidth and Code Size in Computer Systems" PhD thesis, Department of Computer Science and Engineering, Chalmers University of Technology, September 2008. First employment. Google Corp. Mountain View.
M. M. Waliullah: “Techniques to Reduce Inefficiencies in Hardware Transactional Memory Systems”, PhD thesis, Department of Computer Science and Engineering, Chalmers University of Technology, February 2011. First employment. INRIA, Rennes, France.

Licentiate Theses under my supervision: (A Swedish degree that is half-way between M.Sc. and Ph. D. degree.)

Ulf Assarsson: "View Frustum Culling and Animated Ray Tracing: Improvements and Methodological Considerations", Licentiate thesis. May 2001.
Jonas Jalminger. "On Improving Data Cache Space Utilization", Licentiate thesis (main advisor), Jan 2002.
Martin Kampe. "Prediction Methods for Cache and Branch Management in Computers, Licentiate thesis, May 2002.
Peter Rundberg. "Data Dependence Speculation Methods to Expose Thread-Level Parallelism, Nov 2002.
Jochen Hollman “Latency Reduction and Tolerance in Distributed Digital Libraries”, Sept 2003
Md. Mafijul Islam. “Improving Execution Efficiency by Targeting Redundancy and Parallelism”, November 2007
Nima Namaiki. "Exhaustion Dominated Performance: Methodology, Tools, and Empirical Experiments", December 2008
Anurag Negi. “Adaptable Hardware Transactional Memory Protocols,” March 2011.

Teaching

I am teaching Computer Architecture (DAT105) in the 2010/2011 academic year

Professional Services and Activites (2010-2011)

Editor-in-chief of Transactions on HiPEAC

Associate Editor-in-Chief Journal of Parallel and Distributed Computing

Associate editor of IEEE Transactions on Parallel and Distributed Systems

Associate editor of ACM Transactions on Architecture and Code Optimization (TACO)

Organizer of the Fourth Workshop on Programmability issues for Multi-Core Computers (MULTIPROG)

Organizer of the Third Workshop on Multi-Core Computing (MCC 2010)

Program committee member for the 37th IEEE/ACM International Symp. on Computer Architecture. ISCA 2010

Program committee member for the 38th IEEE/ACM International Symp. on Computer Architecture. ISCA 2011

Program committee member for the 17th IEEE High-Performance Computer Architecture. HPCA 2011

Program committee member for the 2012 ACM Int. Conf. on Architectural Support for Programming Languages and Operating Systems. ASPLOS 2012

The Best Part of My Life!!!

My family, i.e., my wife Carina and our wonderful girl Sofia.

Sailing. We just got our dream boat - a Comfort 32.

Jazz. One of my favorites is Pat Metheny

Wine tasting. One of my favorite wine centers in the world is Sonoma

Address information

Email:         pers@chalmers.se

Office address: Department of Computer Science and Engineering

                Chalmers University of Technology

               S-412 96 Gothenburg, SWEDEN

               +46-31-772 1761 (phone)

               +46-31-772 3663 (fax)

                +46-730 346 340 (mobile phone)

                also try +46707 180304 (Nema Labs)

Visiting address: Rännvägen 6

Per Stenström < pers@chalmers.se>

2011-04-05

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