In this project, our goal is to provide timing analysis methods that can make tight but safe estimates of the worst-case execution time (WCET) of programs in the context of pipelined microprocessor systems employing multi-level memory hierarchies. An ultimate goal with this project is to integrate these techniques in compilers so that real-time programs with hard deadlines can exploit the performance potential of high-performance microprocessors. A concrete result so far is an automatic method that can make accurate estimates of WCET on superscalar microprocessors with multi-level memory hierarchies. The major innovation is a concept we call cycle-level symbolic execution. This concept makes it possible to (1) exclude program paths from the analysis that can never be executed and (2) modelling the timing of the remaining paths very accurately. The prototype we have designed to test the approach has been used to demonstrate the strength of our method on a suite of programs. We have shown that it in many cases is possible to achieve exact estimates of the WCET of programs on emerging high-performance microprocessors. This method is important in validating real-time systems in mission-critical applications where timing constraints are necessary for the function. In the trend of using microprocessors in critical control applications, such automated test approaches are key.
Thomas Lunqvist and Per Stenström: "Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques." February 1998. Submitted for Publication.